It is also possible to include all of these different elements in a single file. The stimulus and output checker will be in separate files for larger designs. The stimulus block generates the inputs to the FPGA design and a separate block checks the outputs. The diagram below shows the typical architecture of a simple testbench. Testbenches consist of non-synthesizable VHDL code which generate inputs to the design and checks that the outputs are correct. If you are interested in learning more about testbench design using either VHDL or SystemVerilog, then there are several excellent courses paid course available on sites such as udemy. This allows us to test designs while working through the VHDL tutorials on this site. If you are hoping to design FPGAs professionally, then it will be important to learn this skill at some point.Īs it is better to focus on one language as a time, this blog post introduces basic VHDL testbench principles. System Verilog is widely adopted in industry and is probably the most common language to use. We can write testbenches using a variety of languages, with VHDL, Verilog and System Verilog being the most popular. When using VHDL to design digital circuits, we normally also create a testbench to stimulate the code and ensure that the functionality is correct. Finally, we go through a complete test bench example. We then look at some key concepts such as the time type and time consuming constructs. We start by looking at the architecture of a VHDL test bench. In this post we look at how we use VHDL to write a basic testbench.
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